Method for filling gaps and integrated circuitry

ABSTRACT

A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

TECHNICAL FIELD

[0001] This invention concerns semiconductor processing methods forfilling structural gaps and integrated circuitry having filledstructural gaps.

BACKGROUND OF THE INVENTION

[0002] In semiconductor wafer processing, device structures are formedon a semiconductor substrate. FIG. 6 illustrates a wafer fragment 600comprising a bulk substrate 45 having a pair of wordline constructions60 formed thereon. A gate oxide 15, gate conductor 20, cap 25, andspacers 30 comprise the individual structural components of wordlineconstructions 60. Often, it is desirable to form a layer of insulationmaterial over the device structures formed on a semiconductor wafer,such as substrate 45. An insulation layer 640 on wafer portion 600 maybe formed by depositing borophosphosilicate glass (BPSG) and reflowingthe deposited insulation material to densify and planarize insulationlayer 640.

[0003] Before forming insulation layer 640, a gap exists in areas wheresubstrate 45 is not covered by device structures, like wordlineconstructions 60. Such a gap may expose substrate 45 to boron and/orphosphorous diffusion from the BPSG in insulation layer 640. A barrierlayer 635 is often formed over device structures prior to formation ofinsulation layer 640 to counteract such boron and/or phosphorousdiffusion. Unfortunately, barrier layer 635 forms a reduced gap withinthe original gap that has a higher aspect ratio than the original gap.When the aspect ratio of a gap between device structures is sufficientlyhigh, it may cause formation of voids, such as a void 650, in insulationlayer 640 during deposition. It is highly desirable to form insulationlayer 640 such that it fills the reduced gap between wordlineconstructions 60 without formation of void 650.

[0004] Accordingly, barrier layer 635 addresses the problem of boronand/or phosphorous diffusion, but exacerbates the problem of voidformation. Thus, a need exists to provide a method for protectingagainst boron and/or phosphorous diffusion while reducing the likelihoodof forming voids in structural gaps. Otherwise, semiconductivesubstrates may either suffer defects resulting from boron and/orphosphorous diffusion or defects resulting from formation of voids.

[0005] While motivated from this perspective, the artisan willappreciate other applicabilities, with the invention only being limitedby the accompanying claims appropriately interpreted in accordance withThe Doctrine of Equivalents.

SUMMARY OF THE INVENTION

[0006] According to one aspect of the invention, a semiconductorprocessing method for filling structural gaps includes depositing asubstantially boron free silicon oxide comprising material at a firstaverage deposition rate over an exposed semiconductive material in a gapbetween wordline constructions and at a second average deposition rateless than the first average deposition rate over the wordlineconstructions. A reduced gap having a second aspect ratio less than orequal to a first aspect ratio of the original gap may be provided. Alayer of a boron containing silicon oxide material may be deposited onthe substantially boron free silicon oxide material and over thewordline constructions. The boron containing silicon oxide material maybe deposited in situ in the same chamber.

[0007] According to another aspect of the invention, an integratedcircuit includes a pair of wordline constructions separated by a gaptherebetween in areas where the wordline constructions do not cover anunderlying semiconductive substrate. A layer of substantially boron freesilicon oxide material has a first thickness over the substrate withinthe gap and has a second thickness less than the first thickness overthe wordline constructions. A layer of boron containing silicon oxidematerial is over the substantially boron free silicon oxide comprisingmaterial.

[0008] Other aspects are, of course, contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0010]FIG. 1 is an enlarged sectional view of a wafer portion at oneprocessing step.

[0011]FIG. 2 is an enlarged sectional view of the wafer portion in FIG.1 at a subsequent processing step.

[0012]FIG. 3 is an enlarged sectional view of the wafer portion in FIG.1 at a subsequent processing step.

[0013]FIG. 4 is an enlarged sectional view of the wafer portion in FIG.1 at a subsequent processing step.

[0014]FIG. 5 is an enlarged sectional view of the wafer portion in FIG.2 at a subsequent processing step.

[0015]FIG. 6 is an enlarged sectional view of a prior art wafer portion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0017]FIG. 5 depicts a semiconductive wafer portion 500 of an integratedcircuit according to one aspect of the present invention. Wafer portion500 includes a semiconductive substrate 45 on which a pair of wordlineconstructions 60 have been formed. In the context of this document, theterm “semiconductor substrate” or “semiconductive substrate” is definedto mean any construction comprising semiconductive material, including,but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above. Each wordline construction 60includes a layer of gate oxide 15, a gate conductor 20, an insulativecap 25, and spacers 30 formed on the sidewalls of gate oxide 15, gateconductor 20, and cap 25. Spacers 30 may be formed from a nitrideinsulating material, such as silicon nitride, among other materials.FIG. 1 illustrates wafer portion 100, which may be wafer portion 500 atan earlier point in processing. Notably, a gap 55 in wafer portion 100exists between wordline constructions 60 in an area where wordlineconstructions 60 do not cover substrate 45.

[0018] In wafer portion 500, gap 55 has been lined with a substantiallyboron free silicon oxide comprising material 235 to form a reduced gap255 (shown in FIG. 2) which is, in turn, filled with insulation layer540 of wafer portion 500. In the context of this document,“substantially boron free” and “boron free” mean a boron concentrationfrom 0 atoms/cm³ to no greater than 10¹⁶ atoms/cm³. Example materialsinclude undoped silicon dioxide deposited by decomposition oftetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), or othersilicon oxide comprising materials.

[0019] Even though PSG can be substantially boron free, it may bedesirable in some applications instead to avoid phosphorous diffusioninto substrate 45. Also, it may be desirable to avoid both boron andphosphorous diffusion. Accordingly, a substantially phosphorous free ora substantially dopant free silicon oxide comprising material can beused instead of a substantially boron free material. In the context ofthis document, “substantially phosphorous free” and “phosphorous free”mean a phosphorous concentration from 0 atoms/cm³ to no greater than10¹⁶ atoms/cm³. Similarly, in the context of this document,“substantially dopant free,” “dopant free,” and “undoped” mean a boronconcentration from 0 atoms/cm³ to no greater than 10¹⁶ atoms/cm³ and aphosphorous concentration from 0 atoms/cm³ to no greater than 10¹⁶atoms/cm³.

[0020] Insulation layer 540 is received on boron free material 235 andmay comprise a boron containing, silicon oxide comprising material, suchas borophosphosilicate glass (BPSG) or other silicon oxide comprisingmaterials. In the context of this document, “boron containing” shallmean a boron concentration of greater than 10¹⁶ atoms/cm³. Insulationlayer 540 may be reflowable under conditions similar to those underwhich BPSG is conventionally reflowed.

[0021] In the process of forming an integrated circuit, a devicestructure, such as one of the pair of wordline constructions 60 in FIG.1, are often covered by a material such as insulation layer 540 toprotect the device structure. If insulation layer 540 is boroncontaining, then a risk exists that boron from insulation layer 540 willdiffuse into substrate 45. The boron may affect the operation of devicesformed on substrate 45, such as the pair of wordline constructions 60 orother device structures. To prevent against such diffusion, it ispreferable to form a structure to act as a barrier layer, such as boronfree material 235, preventing boron diffusion into substrate 45.

[0022] Previously, barrier layers increased the aspect ratio of gapsbetween device structures, as in FIG. 6, causing void 650 to form duringdeposition of insulation layer 640. FIG. 6 illustrates this problemalong with its associated text above. Fortunately, the structure ofboron free material 235 in FIG. 5 does not increase the aspect ratio ofgap 55 between wordline constructions 60. That is, boron free material235 has a first thickness in the area over substrate 45 in gap 55 and asecond thickness less than the first thickness over wordlineconstructions 60. In FIG. 5, the second thickness over the wordlineconstructions is zero, however, zero thickness is not required.

[0023] It will be appreciated that boron free material 235, spacers 30,cap 25, gate conductor 20, and gate oxide 15 may possess a variety ofstructures other than the specific structures in FIGS. 1 and 5 and yetaccomplish their individual functions. For example, wafer portion 100includes a bottom border of gap 55 between wordline constructions 60that is defined entirely by substrate 45. Wafer portion also includesside borders of gap 55 that are defined entirely by spacers 30. However,a variety of other configurations are conceivable wherein the bottomborder of gap 55 is not defined entirely by substrate 45 and/or whereside borders of gap 55 are not defined entirely by spacers 30.

[0024]FIG. 5 also indicates that the first thickness of boron freematerial 235, that is, the thickness in the area over substrate 45 ingap 55, is less than the height of gap 55. Accordingly, boron freematerial 235 does not completely fill gap 55. It is conceivable,according to an alternative embodiment of the present invention, thatthe substantially boron free silicon oxide comprising material couldcompletely fill gap 55. It could even exceed the height of gap 55.

[0025] Although a variety of configurations are possible for wordlineconstructions 60, it is preferred that at least a majority portion ofeach side wall of gap 55 is lined with silicon nitride, even though itis not required. FIG. 5 further shows that the boron containing siliconoxide comprising material of insulation layer 540 is received on boronfree material 235. However, it is conceivable that a structure mayinclude insulation layer 540 positioned over boron free material 235,but not received on boron free material 235. It is preferred thatsubstrate 45 be a semiconductive material, such as silicon, but othersemiconductive materials may also be appropriate.

[0026] Another aspect of the present invention further provides avariety of semiconductor processing methods for filling structural gaps.Turning to FIG. 1, such methods may include providing a pair of wordlineconstructions 60 over substrate 45 of semiconductive material. Wordlineconstructions 60 may be separated by a gap 55 exposing thesemiconductive material of substrate 45 therebetween. An exemplary waferportion 100 is illustrated in FIG. 1 and includes all of the elements ofwafer portion 500 shown in FIG. 5, except for boron free material 235and insulation layer 540.

[0027] As an alternative to wordline constructions 60 of wafer portion100, some other device structure could be formed on substrate 45 toprovide a gap 55. Gap 55 may be at least partially bordered by siliconnitride but expose underlying substrate 45. Understandably, a variety ofother configurations are conceivable that would provide a structure inkeeping with the above description.

[0028] Next, a substantially boron free silicon oxide comprisingmaterial may be deposited in gap 55 without increasing the aspect ratioof gap 55. In conventional processes for forming barrier layers theaspect ratio increase produced voids in subsequently depositedinsulation layers. It is an advantage of the present invention that adeposition technique is provided that deposits the required materialsubstantially selectively, at least initially. In the context of thisdocument, “substantially selectively” shall refer to a deposition ratioon the desired versus the undesired surface of greater than 1 to 1. Forexample, the deposition ratio may be at least 1.5 to 1. Deposition mayoccur on semiconductive material, such as silicon, in preference toother material that may be used to form wordline constructions 60, suchas silicon nitride. Selectivity may depend on the process conditions andthe composition of underlying materials receiving the depositedcomposition.

[0029] The selectivity ratio of deposition may be initially 10 to 1 oreven higher. This selectivity ratio may be maintained throughout theformation of boron free material or, in the alternative, the selectivityratio may decrease after a time delay. For example, after a time delayof greater than 5 seconds (sec), the deposition rate over wordlineconstructions 60 may increase such that the selectivity ratio is lessthan 10 to 1. Such deposition rate may even increase sufficiently tomatch the deposition rate over portions of substrate 45 exposed throughgap 55, yielding a later selectivity ratio of 1 to 1. More preferably,the time delay is greater than 100 sec.

[0030] Accordingly, the deposition may occur at a first deposition rateover the silicon of substrate 45 within gap 55 and at a seconddeposition rate over wordline constructions 60. At least initially, thefirst deposition rate may be greater than the second deposition rate. Inthis manner, formation of boron free material may produce a reduced gaphaving an aspect ratio less than or equal to the aspect ratio of gap 55of wafer portion 100. Prior processes for forming barrier layers oftenproduced a reduced gap having an increased aspect ratio in comparison tothe original aspect ratio.

[0031] It is possible that the deposition rate over wordlineconstructions 60 may increase after a time delay to match the depositionrate over exposed substrate 45 within the gap. However, in one aspect ofthe invention, distinction may still be made as to average depositionrate over the respective areas. That is, a first average deposition rateover exposed semiconductive material in gap 55 may be greater than asecond average deposition rate over wordline constructions 60 or otherdevice structures. This is because the second average deposition ratewould include in its calculation the initial period wherein depositionoccurred substantially selective to substrate 45.

[0032] It is theorized that nucleation of deposition products takesplace more readily on a semiconductive substrate, such as silicon, ascompared to nucleation on a wordline construction or other devicestructure, such as a silicon nitride surface. Thus, since a delay in thenucleation occurs on device structure, a time delay in beginningformation of boron free material results. It has also been establishedthat nucleation may be encouraged when a silicon surface is pre-cleanedwith hydrofluoric acid.

[0033] The various deposition techniques described above may beconducted in a thermal chemical vapor deposition chamber or otherprocessing chambers that achieve the stated advantages. As one example,the processing chamber may be a thermal chemical vapor deposition, coldwall, single wafer processor and may be used both to deposit boron freematerial, as well as a doped insulation layer, such as BPSG. Also, asub-atmospheric chemical vapor deposition (SACVD) technique may beparticularly suitable to producing the desired deposition effects.

[0034] Using one such SACVD technique, deposition rates of approximately60 Angstroms per minute (Å/min) over a silicon substrate were obtainedfor undoped silicon dioxide. The deposition rate over silicon nitrideduring the same deposition was initially approximately 0 Å/min for atime delay of about 100 sec. After the initial time delay, theinstantaneous deposition rate over silicon nitride increased to matchthe average deposition rate over the silicon substrate. However, due tothe initial deposition rate of approximately zero, the averagedeposition rate over silicon nitride remained less than the averagedeposition rate over silicon.

[0035] The process conditions needed to produce such a deposition mayvary depending upon the particular deposition chamber, composition ofthe substrates, composition of the deposition reactants, and otherfactors. Generally, however, SACVD may occur at a pressure in thedeposition chamber of about 400 to 760 Torr or, more specifically, at apressure of about 500 to 600 Torr. Temperature may be about 350 to 600degrees Celsius (° C.) or, more specifically, about 450° C. As pressureis decreased within the range indicated, selectivity will tend todecrease. Also, as temperature is decreased within the range indicated,the deposition rate will tend to similarly decrease.

[0036] One example of possible deposition reactants includes acombination of tetraethylorthosilicate (TEOS) and an ozone and oxygen(O₃/O₂) comprising gas. Liquid TEOS may be injected into a depositionchamber at about 200 to 800 milligrams per minute (mg/min) using avaporizer with a helium carrier or, more specifically, at about 300mg/min. Alternatively, a carrier gas, such as helium, may be bubbledthrough liquid TEOS to produce the needed flow into a depositionchamber. TEOS temperature may be approximately 50 to 80° C. and thehelium carrier flow rate may be approximately 0.5 to 1 slm. The ozoneand oxygen comprising gas may include approximately 12 weight percent(wt %) ozone in oxygen. The gas may be fed to a deposition chamber atabout 3 to 7 standard liters per minute (slm) or, more specifically,about 5 slm. The O₃/O₂ may include a diluent, such as helium, at about 5to 9 slm or, more specifically, about 7 slm. Deposition rates on asemiconductive substrate, such as silicon, may vary between about 50 to300 Å/min, but could be even higher.

[0037] Instead of substantially selectively depositing an undopedsilicon dioxide, PSG may be deposited substantially selectively. Byusing a mixture of triethylphosphate (TEPO) and TEOS, a layer of PSGhaving about 3-8 wt % phosphorous may be deposited substantiallyselectively. Flowing of the TEPO into a deposition chamber may occursimilarly to the methods described above. However, the flow rate of TEPOmay be approximately 20 to 150 mg/min. The general deposition conditionsfor SACVD described above also apply.

[0038] Turning now to FIGS. 2-4, three wafer portions are shownexemplifying structures that may result from use of the above-describedmethods. In FIG. 2, wafer portion 200 is illustrated which includes thesame structure depicted in FIG. 1, except that gap 55 of wafer portion100 has been transformed into a reduced gap 255 by deposition of boronfree material 235 in areas where substrate 45 was exposed. Notably, thethickness of boron free material 235 is less than the height of gap 55and no deposition occurred on wordline constructions 60. Accordingly,the aspect ratio of gap 255 may be less than the aspect ratio of gap 55,and yet boron free material 235 protecting against boron diffusion fromany subsequently deposited insulation layer is provided.

[0039] As an example, boron free material 235 may have been formed byconducting SACVD under the conditions specified above where initialdeposition rate is very low or approximately 0 Å/min initially overwordline constructions 60. The deposition may be stopped prior to theend of the time delay that marks the increase in deposition rate overword constructions 60 to prevent boron free material formation over wordconstructions 60.

[0040]FIG. 3 could exemplify formation of a wafer portion where thedeposition continued past the time delay that marked the increase indeposition rate over wordline constructions 60. Thus, the averagedeposition rate over exposed portions of substrate 45 may be greaterthan the average deposition rate over wordline constructions 60. Suchmay produce a boron free material 335 having a greater thickness overgap 55 compared to the thickness over wordline constructions 60.Accordingly, wafer portion 300 of FIG. 3 illustrates a reduced gap 355having an aspect ratio less than, or perhaps equal to, the aspect ratioof gap 55 of wafer portion 100 in FIG. 1. Depending on the originalaspect ratio of gap 55 and the thickness of boron free material 335 onspacers 30, reduced gap 355 could have an aspect ratio greater gap 55.However, the aspect ratio of gap 355 would certainly be less thanotherwise using a conventional deposition process.

[0041] Alternatively, boron free material 335 of wafer portion 300 couldhave been formed in a deposition process which did not have an initialtime delay during which the deposition rate over wordline constructions60 was very low or approximately 0 Å/min. Rather, the deposition processmay have occurred substantially selectively to substrate 45 such thatboron free material 335 simply deposited over substrate 45 at a higherinstantaneous rate than over wordline constructions 60.

[0042] Turning to FIG. 4, a wafer portion 400 is illustrated includingall the same elements of wafer portion 100 shown in FIG. 1, except thatgap 55 has been filled with a boron free material 435. Notably, boronfree material 435 completely fills the original gap 55 of wafer portion100. Gap 55 is completely filled and a portion of boron free material435 extends over wordline constructions 60. Thus, a layer of insulationmay subsequently be formed over wafer portion 600 without concern forthe creation of undesirable voids in gaps having too high of an aspectratio.

[0043] If boron free material 435 comprised PSG then, conceivably, boronfree material 435 could simultaneously comprise an insulation layer,such as insulation layer 540 of wafer portion 500 in FIG. 5. Such may beless desirable if a portion of the boron free material extends over thewordline constructions or other device structure and if planarization isthus warranted. However, the height of a device structure and thedeposition conditions could conceivably be coordinated. Withcoordination, gap 55 could become completely filled by boron freematerial at the point in processing where deposition of boron freematerial first begins to occur over the device structure. Thus, theboron free material may continue upward to a height suitable for boronfree material to simultaneously function as a planarized insulationlayer. One disadvantage of such a PSG insulation layer is that it mightnot be possible to reflow in the event that planarization is notinitially achieved.

[0044] The thickness of any boron free material formed over substrate 45to prevent boron diffusion into substrate 45 may vary widely dependingupon the degree of protection desired for a particular application. Evena very thin layer of boron free material, such as 1.0 Å, may providesome protection from boron diffusion. However, generally, the more thickthe boron free material the more protection it may provide from borondiffusion. For most applications, boron free material having a thicknessof 100 to 300 Å in the area over an exposed portion of substrate 45 issufficient. More specifically, a film thickness of 200 Å is mostfrequently selected.

[0045] Thus, assuming a 200 Å boron free material thickness, a 60 Å perminute deposition rate over substrate 45, and a 100 sec time delaybefore deposition over wordline constructions 60, the layer formed mayhave a structure similar to that shown in FIG. 3 for boron free material335. That is, deposition may occur on substrate 45 within gap 55illustrated in FIG. 1 without deposition of any substantial amount ofmaterial on wordline constructions 60 for the first 100 sec. Up to thetime delay, the boron free material may have a structure similar to thatshown for boron free material 235 in FIG. 2. Once processing continuesbeyond 100 sec, material may be deposited on wordline constructions 60and over substrate 45 at the same deposition rate. Accordingly, thestructure of the boron free material may resemble the structure of boronfree material 335 shown in FIG. 3. After 200 sec, the 60 Å/mindeposition rate may produce a boron free material thickness of about 200Å in the area over substrate 45 and a thickness of about 100 Å overwordline constructions 60.

[0046] In the above example, reduced gap 355 would have a height about200 Å less than the height of gap 55 and a width also about 200 Å lessthan the original width. If a conventional method were used instead toform boron free material 635 of wafer portion 600 in FIG. 6, then theheight of gap 55 would be reduced by about 200 Å and the width would bereduced by about 400 Å.

[0047] Assuming gap 55 had a height of 0.125 micrometers (μm) and awidth of 0.5 μm, the aspect ratio would be 0.25. Under the above exampleof reduced gap 355, aspect ratio would be reduced to 0.24 in forming theboron free material as described. A conventional process would increasethe aspect ratio to 0.27. Assuming gap 55 had a height of 0.25 μm and awidth of 0.5 μm, the aspect ratio would be 0.5. Under the above exampleof reduced gap 355, aspect ratio would remain unchanged at 0.5. With aconventional process, aspect ratio would increase to 0.54. Assuming gap55 had a height of 0.5 μm and a width of 0.25 μm, aspect ratio wouldequal 2.0, which the above example of reduced gap 355 would increase to2.1 and a conventional process would increase to 2.4.

[0048] Accordingly, comparing the above example to a conventionalprocess, aspect ratio produced by a conventional process is higher ineach case than aspect ratio produced by the present invention. For gapshaving an initial aspect ratio of 0.25, the above example reduced theaspect ratio while a conventional process increased aspect ratio. For aninitial aspect ratio of 0.5, the above example did not change aspectratio and a conventional process increased aspect ratio. For an initialaspect ratio of 2.0, the above example increased aspect ratio, but to alesser degree than aspect ratio would be increased by a conventionalprocess. One of ordinary skill will recognize that such comparisons aredependent on the particular numeric values selected for gap dimensionsand boron free material thicknesses. Accordingly, they are provided forillustration and not necessarily to define a mathematical relationship.

[0049] Understandably, whether an aspect ratio of a gap is increased ordecreased may depend upon the magnitude of the aspect ratio originallyas well as the magnitude of thickness for the boron free material overboth substrate 45 and wordline constructions 60 or other devicestructure. However, the aspect ratio of a reduced gap, according to thepresent invention, bears the advantage of being less than the aspectratio of a reduced gap produced by a conventional process.

[0050] The methods according to the present invention discussed abovemay be followed by deposition of a boron containing silicon oxidecomprising material, such as BPSG, to form an insulation layer. Such adeposition of insulation layer 540 over wafer portion 200 of FIG. 2 mayproduce wafer portion 500 of FIG. 5. Generally, depositing an insulationlayer may occur at the same deposition rate over any partially orcompletely filled gap and any wordline constructions or other devicestructure. Nevertheless, it remains conceivable that deposition couldoccur in some selective fashion in keeping with the principles describedabove. It may further be desirable to deposit the insulation layer insitu in the same deposition chamber where any boron free material wasformed.

[0051] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method for filling structural gapscomprising: providing a pair of wordline constructions over asemiconductive material substrate, the wordline constructions beingseparated by a gap and exposing semiconductive material therebetween;depositing a substantially boron free silicon oxide comprising materialat a first average deposition rate over the exposed semiconductivematerial between the wordline constructions and at a second averagedeposition rate less than the first average deposition rate over thewordline constructions; and depositing a layer of a boron containingsilicon oxide comprising material on the substantially boron freesilicon oxide comprising material and over the wordline constructions.2. The method of claim 1, wherein the pair of wordline constructionscomprise conductive gates having sidewalls which are at least partiallycovered with silicon nitride and which border at least a portion of thegap.
 3. The method of claim 2, wherein the silicon nitride covers atleast a majority portion of the gate sidewalls and borders at least amajority portion of the gap.
 4. The method of claim 2, wherein a bottomborder of the gap is defined entirely by the semiconductive material andside borders of the gap are defined entirely by silicon nitrideencapsulation of the wordline constructions.
 5. The method of claim 1,wherein the semiconductive material comprises silicon.
 6. The method ofclaim 1, wherein the depositing the substantially boron free materialcomprises a sub-atmospheric chemical vapor deposition (SACVD).
 7. Themethod of claim 6, wherein the SACVD deposition occurs at a pressure ofabout 400 to 760 Torr and a temperature of about 350 to 600 Celsius (°C.) while providing about 200 to 800 milligram/minute (mg/min) of atetraethylorthosilicate comprising liquid and providing about 4.5 to 7standard liters/minute (slm) of an ozone and oxygen comprising gas. 8.The method of claim 1, wherein the boron free material comprises undopedsilicon dioxide or phosphosilicate glass.
 9. The method of claim 8,wherein the boron free material comprises phosphosilicate glass andcompletely fills the gap.
 10. The method of claim 1, wherein the boronfree material does not completely fill the gap.
 11. The method of claim1, wherein the second average deposition rate is initially approximatelyzero Å/min and begins to increase after a time delay.
 12. The method ofclaim 11, wherein the time delay is greater than 5 seconds.
 13. Themethod of claim 11, wherein the time delay is greater than 100 seconds.14. The method of claim 1, wherein the depositing a boron containingmaterial occurs at the same deposition rate over the gap and thewordlines.
 15. The method of claim 1, wherein the boron containingmaterial comprises a borophosphosilicate glass (BPSG).
 16. Asemiconductive processing method for filling structural gaps comprising:forming a device structure having a gap at least partially bordered bysilicon nitride and that exposes an underlying silicon comprisingsubstrate, the gap having a first aspect ratio; depositing asubstantially boron free silicon oxide comprising material substantiallyselectively, at least initially, to the silicon substrate to form areduced gap having a second aspect ratio less than or equal to the firstaspect ratio; and depositing a layer of boron containing silicon oxidecomprising material on the substantially boron free silicon oxidecomprising material and over the device structure.
 17. The method ofclaim 16, wherein the device structure is comprised of a pair of spacedconductive device components at least partially encapsulated by siliconnitride.
 18. The method of claim 17, wherein at least a majority portionof each sidewall of the gap is lined with the silicon nitride.
 19. Themethod of claim 17, wherein the conductive device components compriseconductive polysilicon comprising lines.
 20. The method of claim 17,wherein a bottom border of the gap is defined entirely by the siliconsubstrate and side borders of the gap are defined entirely by siliconnitride encapsulation of the conductive device components.
 21. Themethod of claim 16, wherein depositing a boron free material comprises aSACVD.
 22. The method of claim 16, wherein the boron free materialcomprises undoped silicon dioxide or phosphosilicate glass.
 23. Themethod of claim 16, wherein the boron containing material comprises aBPSG.
 24. A semiconductor processing method for filling structural gapscomprising: providing a pair of wordline constructions over a siliconsubstrate, the wordline constructions being separated by a gap andexposing the silicon substrate therebetween; depositing a substantiallyboron free silicon oxide comprising material substantially selectively,at least initially, to the silicon substrate in a thermal chemical vapordeposition chamber; and depositing in situ in the chamber, a BPSG on thesilicon oxide comprising material.
 25. The method of claim 24, whereinthe pair of wordline constructions comprise conductive gates havingsidewalls which are at least partially covered with silicon nitride andwhich border at least a portion of the gap.
 26. The method of claim 25,wherein the silicon nitride covers at least a majority portion of thegate sidewalls and borders at least a majority portion of the gap. 27.The method of claim 25, wherein a bottom border of the gap is definedentirely by the silicon substrate and side borders of the gap aredefined entirely by silicon nitride encapsulation of the wordlineconstructions.
 28. The method of claim 24, wherein the depositing aboron free material comprises a SACVD.
 29. The method of claim 24,wherein the boron free material comprises silicon dioxide orphosphosilicate glass
 30. The method of claim 24, wherein the boron freematerial does not completely fill the gap.
 31. The method of claim 24,wherein the deposition of the boron free material initially occurssubstantially selectively to the silicon when compared to deposition ona silicon nitride layer received over the pair of wordlines.
 32. Themethod of claim 31, wherein the deposition occurs on the siliconcompared to the silicon nitride at an average selectivity ratio greaterthan
 1. 33. The method of claim 24, wherein the depositing the BPSGoccurs at the same deposition rate over the gap and the wordlines.
 34. Asemiconductor processing method for filling structural gaps comprising:providing a pair of wordline constructions over a silicon substrate, thewordline constructions being separated by a gap exposing the siliconsubstrate therebetween and comprising silicon nitride which at leastpartially lines the gap; and depositing a substantially boron freesilicon oxide comprising material at a first deposition rate over thesilicon substrate within the gap and at a second deposition rate overthe wordline constructions, wherein, at least initially, the firstdeposition rate is greater than the second deposition rate.
 35. Themethod of claim 34, wherein the silicon nitride lines at least amajority of the gap.
 36. The method of claim 34, wherein a bottom borderof the gap is defined entirely by the silicon substrate and side bordersof the gap are defined entirely by the silicon nitride encapsulation.37. The method of claim 34, further comprising depositing a boroncontaining silicon oxide comprising material on the boron free siliconoxide comprising material.
 38. The method of claim 34, wherein the stepof depositing a boron free material comprises a SACVD.
 39. The method ofclaim 34, wherein the boron free material comprises undoped silicondioxide or phosphosilicate glass.
 40. The method of claim 34, whereinthe boron free material does not completely fill the gap.
 41. The methodof claim 34, wherein the boron free material completely fills the gap.42. The method of claim 41, wherein the boron free material comprisesphosphosilicate glass.
 43. The method of claim 34, wherein the seconddeposition rate is initially approximately zero Å/min and increases tothe first deposition rate after a time delay.
 44. The method of claim43, wherein the time delay is greater than 5 seconds.
 45. The method ofclaim 43, wherein the time delay is greater than 100 seconds.
 46. Anintegrated circuit comprising: a) a semiconductive substrate; b) a pairof wordline constructions on selected portions of the substrate, thewordline constructions comprising silicon nitride sidewall spacers andbeing separated by a gap therebetween in areas where the wordlineconstructions do not cover the substrate; c) a layer of substantiallyboron free silicon oxide comprising material having a first thicknessover the substrate within the gap and having a second thickness lessthan the first thickness over the wordline constructions; and d) a layerof boron containing silicon oxide comprising material over thesubstantially boron free silicon oxide comprising material.
 47. Theintegrated circuit of claim 46, wherein the boron containing material isreceived on the substantially boron free silicon oxide comprisingmaterial.
 48. The integrated circuit of claim 46, wherein at least amajority portion of each sidewall of the gap is lined with the siliconnitride.
 49. The integrated circuit of claim 46, wherein a bottom borderof the gap is defined entirely by the substrate and side borders of thegap are defined entirely by silicon nitride of the wordlineconstructions.
 50. The integrated circuit of claim 46, wherein thesemiconductive substrate comprises silicon.
 51. The integrated circuitof claim 46, wherein the first thickness is less than a height of thegap.
 52. The integrated circuit of claim 46, wherein the boroncontaining material comprises a BPSG.
 53. The integrated circuit ofclaim 46, wherein the boron free material completely fills the gap. 54.The integrated circuit of claim 46, wherein the boron free material doesnot completely fill the gap.
 55. The integrated circuit of claim 46,wherein the boron free material comprises undoped silicon dioxide. 56.The integrated circuit of claim 46, wherein the boron free materialcomprises phosphosilicate glass.
 57. The integrated circuit of claim 46,wherein the boron free material is received on the semiconductivesubstrate with the gap.